Simulation has long been an essential step in the design and manufacture of microelectronic circuits and systems. Present day Ultra-Large Scale Integration (ULSI) devices may include hundreds of thousands or millions of active electronic devices ("transistors") on an integrated circuit chip, which are interconnected on the chip to perform a particular function. The large capital investment required to fabricate microelectronic devices and the difficulty in reworking microelectronic devices which do not operate as planned, have produced the need to simulate circuit performance before manufacture.
Accordingly, many simulators have been developed and marketed. One widely used circuit simulator is a program which was developed at the Electronics Research Laboratory of the University of California, Berkeley, known as SPICE. In general, SPICE is a system for simulating nonlinear circuits in time, using nonlinear time-independent generalized admittance representations. A popular version of SPICE (SPICE 2) is described in "SPICE Version 2G.6 User's Guide" Berkeley: University of California, Department of Electrical Engineering and Computer Science, 1980 by Vladimirescu et al.
Circuit simulators have also been the subject of patent protection because they are an integral part of the design and fabrication of microelectronic devices. Recently issued patents concerning circuit simulators are U.S. Pat. No. 4,918,643 to Wong entitled Method and Apparatus for Substantially Improving the Throughput of Circuit Simulators; U.S. Pat. No. 5,047,971 to Horwitz entitled Circuit Simulation; and U.S. Pat. No. 5,051,911 to Kimura et al. entitled Apparatus for Effecting Simulation of a Logic Circuit and Method for Producing a Semmiconductor Device Using the Simulation Approach.
Circuit simulators are typically software based, and are designed to accept a description of the circuit which defines the circuit topology and element values. Each element in the circuit is typically specified by an element line containing the element name, the connecting nodes, and electrical parameter values. Simulators typically simulate circuits which contain passive devices such as resistors, capacitors, diodes, inductors and mutual inductors; stimuli, such as voltage and current sources, and active devices such as bipolar junction transistors (BJT), junction field effect transistors (JFET) and metal oxide semiconductor field effect transistors (MOSFET). The simulator can typically be configured to perform DC analysis, AC small signal analysis and transient analysis.
As the feature sizes of integrated circuits continue to shrink, and operating speeds increase, the characterization of the parasitic effects associated with the interconnect circuit becomes more critical and more difficult. In the past, the delays caused by the interconnects could simply be disregarded when simulating the behavior of the entire integrated circuit. This was because the microelectronic circuit's functional logic devices including logic gates dominated the simulation profile in terms of overall delay. However, as the feature sizes of integrated circuits continue to shrink, the resistance of the circuit's interconnections per unit length increases. This causes an increase in delay, or otherwise offsets the speed advantages obtained using devices having smaller feature sizes.
In addition, the close proximity of metal lines makes the component cross-talk capacitance larger. Even inductance effects, which are evident for boards and multichip modules which comprise microelectronic systems, may be important for modeling the integrated circuit packaging or chip to package interface. Accordingly, a complete circuit simulation of an integrated circuit must now account for the resistive, inductive and capacitive effects of the interconnect paths in addition to simulating the effect of the logic gates and other functional logic devices.
It will be understood by those having skill in the art that a conventional circuit simulator, such as SPICE, could be used for a complete simulation of a microelectronic circuit, including the logic devices and the interconnect paths. However, because of the large numbers of circuit elements in the interconnect portion of the circuit, a complete simulation may become extremely time consuming, and may exceed the storage capabilities of the processing system on which the simulation is run.
A major improvement in the simulation of linear interconnects is described in a publication by Lawrence T. Pillage and Ronald A. Rohrer entitled Asymptotic Waveform Evaluation for Timing Analysis, IEEE Transactions on Computer-Aided Design, Vol. 9, No. 4, April 1990, pp. 352-366, the disclosure of which is hereby incorporated herein by reference. Described is an Asymptotic Waveform Evaluation (AWE) methodology to provide a generalized approach to linear resistor-inductor-capacitor (RLC) circuit or system response approximations. AWE is a general method for computing a qth order approximate model of a circuit or system, and can be obtained by computing 2g moments of the circuit or system and matching these moments to the circuit's or system's impulse response. The moments, in their simplest interpretation, represent the coefficients of the powers of s in the Taylor series expansion of the homogeneous circuit response. Once the desired number of moments is found, they may be mapped to the approximate dominant poles of the lower order approximating system. The corresponding residues are then computed using the poles and moments. Once the residues of the approximate response are found, the time domain response of an interconnect circuit, for example, may be determined.
In the AWE technique, moments of a circuit may be generated by successively solving an equivalent DC circuit with all capacitors replaced by current sources and all inductors replaced by voltage sources. The resulting voltages across the capacitors and currents through the inductors comprise one generation of circuit moments. Initially, all capacitor-current sources and inductor-voltage sources are set to zero, and independent voltage and current sources of the actual circuit are set to their final values. For subsequent moment generations, each capacitor-current source is set to the product of its capacitance and its previous moment, while each inductor-voltage source is set to the product of its inductance and its previous moment. This process may be continued until the desired order of approximation is obtained. It has been shown that, for large numbers of interconnects, AWE can provide more than a hundredfold speed increase compared to a conventional SPICE circuit simulation.
In order to provide a complete analysis of a microelectronic circuit, not only must the behavior of the linear interconnects be included, the behavior of the nonlinear portions of the circuit must be included as well. Typical nonlinear aspects of a microelectronic circuit include, for example, the presence of nonlinear drivers, nonlinear loads and nonlinear transmission elements such as pass transistors, as part of the circuit. The occurrence of these types of nonlinear aspects in conjunction with the interconnect circuit is especially prevalent in present-day technologies where a single interconnect net can be expected to travel through a nonlinear buffer, through chip-packaging to traces on a multi-chip module (MCM) or printed circuit board (PCB), and back onto a another integrated circuit through packaging and to a nonlinear load, for example. Thus, while interconnect problems are largely linear, complete analysis requires the inclusion of the nonlinear portions of the interconnect circuit as well.
The AWE technique, however, is limited to the solution of linear circuits only. Consequently, improved techniques for solving nonlinear portions of the circuit in conjunction with the interconnect circuit need to be developed to provide accurate transient analysis of the entire microelectronic circuit.